1. Technical Field
The disclosure generally relates to a semiconductor technology, and more particularly, to a semiconductor chip including a spare bump and a stacked package having the same.
2. Related Art
In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demands toward miniaturization and mounting reliability. In recent years, as miniaturization and high performance are demanded in electric and electronic products, various stacking techniques have been developed.
The term “stack” as used in the semiconductor industry means to pile vertically two or more semiconductor chips or semiconductor packages. With these stacking technologies, a memory element may have a memory capacity two or more times greater than that obtainable through semiconductor integration process. Besides the increased memory capacity, the stacked packages also have advantages in terms of mounting density and efficient utilization of a mounting area. For these reasons, research and development for stacked packages have been accelerated.
As an example of a stacked package, a stacked package has been introduced in which through electrodes and bumps are formed such that upper and lower semiconductor chips are electrically connected with one another by the through electrodes and bumps. The stacked package has an advantage in that high operation speed and miniaturization can be achieved since signals are transferred through vertical input/output lines formed by the through electrodes and bumps.